1. Field of the Invention
The invention relates to an electrostatic discharge protective circuit formed by use of a silicon controlled rectifier, and in particular to an electrostatic discharge protective circuit which can efficiently protect an internal circuit from damage by lowering the trigger voltage of the silicon controller rectifier.
2. Description of the Related Art
Currently, in ICs processes including a deep sub-micron IC process, an electrostatic discharge has been a main factor to cause IC damage. To overcome the problem of the electrostatic discharge, on-chip electrostatic discharge protective circuits are designed to connect input/output ports. However, the electrostatic discharge protective circuits can not provide a sufficient protective capability in line with continuous developments of the IC processes. Therefore, it is urgently desired to enhance the efficiency of the electrostatic discharge protective circuits in semiconductor industry.
In general, each electrostatic discharge protective circuit has characteristics of a high critical voltage, a small lay-out area and a low RC delay. Since silicon controller rectifiers have a high current sinking/sourcing capability, a low turn-on impedance, a low power consumption and a high heat dissipation capability, they are widely used to form electrostatic discharge protective circuits.
Referring to FIG. 1, there is shown an electrostatic discharge protective circuit formed by use of a traditional silicon controller rectifier 10. In FIG. 1, electrostatic charges, so-called over-stress, on an input port (I/P) can be discharged via the traditional silicon controller rectifier 10 to ground Vss. Thus, the electrostatic charges cannot flow into an internal circuit 14 via a buffer input gate 12 to damage the internal circuit 14.
FIG. 2 is a cross-sectional view of the traditional silicon controller rectifier 10 of FIG. 1. FIG. 3 is an equivalent circuit diagram of the traditional silicon controller rectifier 10 of FIG. 2. As shown in FIGS. 2 and 3, a P.sup.+ -type diffusion region 20, an N.sup.+ -type well 21 and a P-type substrate 22 form a parasitic PNP bipolar junction transistor B1. An N-type well 21, a P-type substrate 22 and an N.sup.+ -diffusion region 23 form a parasitic NPN bipolar junction transistor B2. An equivalent resistor R1 is formed between the P-type substrate 22 and a P.sup.+ -type diffusion region 24. The P.sup.+ -type diffusion region 20 and an N+-type diffusion region 25 are electrically coupled to the input port (I/P). Furthermore, the base of the PNP bipolar junction transistor B1 is electrically coupled to the collector of the NPN bipolar junction transistor B2. The collector of the PNP bipolar junction transistor B1 and the base of the NPN bipolar junction transistor are electrically coupled to the ground Vss via the resistor R1. Thus, the traditional silicon controller rectifier 10 is completely formed. The silicon controller rectifier 10 performs an electrostatic discharge by creating a punch-through effect. For example, the punch-through effect is triggered by a breakdown between the N-type well 21 and the P-type substrate 22. However, a trigger voltage larger than 10V, or even as many as 25V, is required. Therefore, it is not suitable for the deep sub-micron semiconductor process.
In order to attain the preferable function of the electrostatic discharge protection, the trigger voltage of the electrostatic discharge protective circuit must be smaller than the breakdown voltage of the buffer input gate 12. Although, the traditional silicon controller rectifier is widely used for the electrostatic discharge, its trigger voltage is much higher. As we know that the smaller the sizes of semiconductor devices, the lower the operating voltage. Therefore, when electrostatic charges are applied on the input port, it is possible that the over stress, smaller than the trigger voltage of the electrostatic discharge protective circuit, is large enough to damage the internal circuit.